An all-digital phase locked loop (ADPLL) generally comprises a digitally controlled oscillator (DCO), a digital loop filter that applies a multiple bit control word to the DCO, a digital adder with an output that feeds the input of the loop filter and a first input that receives a digital reference input, and a digital divider for dividing the output of the oscillator and applying the divided oscillator output to a second, subtracting input of the digital adder. Since the smallest possible frequency step with such an ADPLL is given by the frequency of the reference input, fractional division has been introduced by incorporating in the loop a sigma-delta modulator which modulates the division ratio. See Kozak et al., “A Pipelined Noise Shaping Coder for Fractional-N Frequency Synthesis,” IEEE Transactions on Instrumentation and Measurement, Vol. 50, No. 5, October 2001. This document also discloses a multi-stage noise shaping (MASH) technique for a sigma-delta modulator.